A general task in chip fabrication and in the manufacturing of an integrated circuit may be the scaling of the included structure elements to a smaller feature size. Reducing the feature size of the structure elements of a chip may lead to a reduced reproducibility, since the error tolerance during fabrication may become smaller, due to the small dimensions of the structure elements. As a direct result of the scaling, the number of structure elements on a single chip or a single die may increase. As a result, testing a structure element on a chip, the functionality of an integrated circuit, as well as finding a critical process parameter and the critical dimension of a structure element may become important, and hence, a test structure may be used, which may be arranged within an integrated test circuit or within a chip, e.g. a test chip. Since the number of test structure elements included in an integrated test circuit may be very large, e.g. larger than 100 or larger than 1000 or even larger, providing a likewise large number of contact pads for electrically contacting the test structure elements may be a problem, since typical test devices may only have a limited number of pins which can be connected to the contact pads. This limitation may be mainly caused by the use of large space consuming structures, which may be necessary for connecting a large number of pins with the corresponding contact pads compared to the small size of a test structure element within an integrated test circuit. The number of desired test structures (or test structure elements) may increase with increasing number of metallization layers included in an integrated circuit. Therefore, problems may occur regarding the electrically contacting of the individual test structure elements. Despite the fact that contact pads may be provided for every test structure element, the number of pins (e.g. spring-loaded pins, e.g. pogo pins) provided in a test device (e.g. provided in a so-called bed of nails tester) may be limited. Further, also the necessary space on a wafer (e.g. in a kerf region of a wafer) to form a large number of contact pads for a test structure may be limited.